Will Join a multi-tasking dynamic team and take part in the development and debug of future HDBaseT products.
Main Interfaces in/outside Valens: R&D team.
- BSc/MSc in Electrical Engineering – from a well-known university.
- At least 5 Years of experience as VLSI designer.
- Verilog Knowledge (design, debug) – must.
- Experience with Specman – an advantage.
- FPGA experience – an advantage.