Will Join a multi-tasking dynamic team. Will be In charge of planning (architecture) and developing (coding) all the needed simulation environments for tests and debugs. The simulation environments are used to develop new RTL blocks, Full-chip integration, FPGA code and also to debug and resolve bugs found.
- BSC in Electrical Engineering
- At least 3 years’ experience as a verification engineer.
- Knowledge in Specman – an advantage.
- Knowledge in UVM – an advantage