- In charge of planning (architecture) and developing (coding) all the needed simulation environments for tests and debugs.
- The simulation environments are used to develop new RTL blocks, Full-chip integration, FPGA code and also to debug and resolve bugs found.
- BSC in Electrical Engineering – from a well-known university
- At least 4 years’ experience as verification engineer
- Knowledge in specman – an advantage
- Knowledge in uvm – an advantage