R&D
Verification Engineer

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Job Description

  • In charge of planning (architecture) and developing (coding) all the needed simulation environments for tests and debugs.
  • The simulation environments are used to develop new RTL blocks, Full-chip integration, FPGA code and also to debug and resolve bugs found.

Job Requirements

  • BSC in Electrical Engineering
  • At least 3 years’ experience
  • Knowledge in specman – an advantage.
  • Knowledge in uvm – an advantage.

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