R&D

Senior Verification Engineer

Israel | Valens HQ | Updated: April 12, 2021

Apply for this position

    Valens is committed to protecting and respecting your privacy. We would like to contact you about our products and services, as well as other content that may be of interest to you. You may unsubscribe from these communications at any time.

    For more information on how we are committed to protecting your privacy, please review our Privacy Policy.

    Job Description

    In charge of planning (architecture) and developing (coding) all the needed simulation environments for tests and debugs.

    The simulation environments are used to develop new RTL blocks, Full-chip integration, FPGA code and also to debug and resolve bugs found.

    Job Requirements

    • BSC in Electrical Engineering – from a well-known university.
    • At least 5 years’ experience.
    • Knowledge in Specman – an advantage.
    • Knowledge in UVM – an advantage.

    Apply for this position

      Valens is committed to protecting and respecting your privacy. We would like to contact you about our products and services, as well as other content that may be of interest to you. You may unsubscribe from these communications at any time.

      For more information on how we are committed to protecting your privacy, please review our Privacy Policy.

      More open R&D positions

      R&D
      DSP/Algorithms Engineer
      Learn more
      R&D
      Verification Engineer
      Learn more
      R&D
      Automation Engineer – Student Position
      Learn more
      Top